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| PRODUCT SPECIFICATIONS (R) Integrated Circuits Group LH28F320BJE-PTTL90 32M (2M x 16/4M x 8) (Model No.: LHF32J02) Flash Memory Spec No.: EL124011 Issue Date: April 17, 2000 SHARP LHF32JO2 l Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l When using the products covered herein, please observe the conditions written herein and the . precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). *Office electronics .t l Instrumentation and measuring equipment *Machine tools *Audiovisual equipment *Home appliance @Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. *Control and safety devices for airplanes, trains, automobiles, transportation equipment *Mainframe computers *Traffic control systems l Gas leak detectors and automatic cutoff devices *Rescue and security equipment *Other safety devices and safety equipment, etc. and other -- (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. *Aerospace equipment l Communications equipment for trunk lines *Control equipment for the nuclear power industry *Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. l Please direct all queries regarding the products covered herein to a sales representative of the company. Rev. 1.26 SHARI= LHF32JO2 1 CONTENTS PAGE 1 INTRODUCTION.. ............................................................ 3 3 5 DESIGN CONSIDERATIONS PAGE ....................................... 27 1.1 Features ........................................................................ 5.1 Three-Line Output Control ........................................ 27 5.2 RY/BY# and WSIM Polling ....................................... 27 5.3 Power Supply Decoupling ......................................... 27 5.4 V,, Trace on Printed Circuit Boards ..................... 27 RP# Transitions .................................... 27 Protection.. ..................................... 28 28 5.5 V,, . V,,,, 1.2 Product Overview.. ...................................................... .3 1.3 Product Description.. .................................................... 4 1.3.1 Package Pinout .: .......................... ...... ..- . .............. 4 .... 1.3.2 Block Organization ................................................ .4 2 PRINCIPLES OF OPERATION.. ..................................... .8 2.1 Data Protection.. .......................................................... .8 3 BUS OPERATION ........................................................... .9 3.1 Read .............................................................................. 3.3 Standby ......................................................................... 3.4 Reset ............................................................................. 9 9 9 3.2 Output Disable.. ........................................................... .9 5.6 Power-Up/Down 5.7 Power Dissipation ...................................................... 5.8 Data Protection Method.. ........................................... 28 6 ELECTRICAL SPECIFICATIONS ................................ 29 29 29 31 6.1 Absolute Maximum Ratings ...................................... 29 6.2 Operating Conditions.. ............................................... 6.2.1 Capacitance.. ........................................................ 6.2.3 DC Characteristics.. ............................................. 6.2.2 AC Input/Output Test Conditions ........................ 30 6.2.4 AC Characteristics - Read-Only Operations.. ...... 33 6.2.5 AC Characteristics - Write Operations ................ 36 6.2.6 Alternative CE#-Controlled Writes.. .................... 38 6.2.7 Reset Operations .................................................. 40 3.5 Read Identifier Codes.. ............................................... 10 3.6 OTP(One Time Program) Block.. .............................. 10 3.7 Write.. ......................................................................... 1COMMAND DEFINITIONS.. 11 ......................................... 11 4.1 Read Array Command.. .............................................. 13 4.2 Read Identifier Codes Command ............................... 13 4.3 Read Status Register Command.. ............................... 13 4.4 Clear Status Register Command.. ............................... 13 4.5 Block Erase Command.. ............................................. 14 4.6 Full Chip Erase Command.. ....................................... 14 4.7 Word/Byte Write Command.. ..................................... 14 4.8 Block Erase Suspend Command ................................ 15 4.9 Word/Byte Write Suspend Command.. ....................... 15 4.10 Set Block and Permanent Lock-Bit Command.. ....... 16 4.11 Clear Block Lock-Bits Co mmand.. .......................... 16 4.12 OTP Program Command .......................................... 17 4.13 Block Locking by the WP# ...................................... 17 6.2.8 Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration Performance ................. 41 7 PACKAGE AND PACKING SPECIFICATIONS .. .... ... . 42 Rev. 1.26 SHAI?P LHF32JO2 2 LH28F320BJE-PTTL90 32M-BIT ( 2Mbit x16 / 4Mbit x8 ) Boot Block Flash MEMORY I I I I I I Low Voltage Operation Single Voltage - v cc =v ,,=2.7V-3.6V OTP(One Time Program) Block 3963 word + 4 word Program only array n Enhanced Automated Suspend Options Word/Byte Write Suspend to Read Block Erase Suspend to Word/Byte Write Block Erase Suspend to Read I Enhanced Data Protection Features Absolute Protection with VccwSVcm, Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration Lockout during Power Transitions Block Locking with Command and WP# Permanent Locking User-Configurable 90ns(Vcc=2.7V-3.6V) x8 or x 16 Operation High-Performance Read Access Time Operating Temperature 0C to +7O"C Low Power Management Typ. 4pA (Vcc=3.0V) Standby Current Automatic Power Savings Mode Decreases I,-, Static Mode Typ. 12OpA (Vc,=3.0V, TA=+25"C, f=32kHz) Read Current in n Automated Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration Command User Interface (CUI) Status Register (SR) Write Interface n SRAM-Compatible 4%Lead TSOP I Optimized Array Blocking Architecture Two 4K-word (8K-byte) Boot Blocks Six 4K-word @K-byte) Parameter Blocks Sixty-three 32K-word (64K-byte) Main Blocks Top Boot Location H Industry-Standard Packaging n ETOXTM* Nonvolatile Flash Technology n CMOS Process (P-type silicon substrate) n Not designed or rated as radiation hardened I Extended Cycling Capability Minimum 100,000 Block Erase Cycles IHARP's LH28F320BJE-P'TTL90 vide range of applications. Flash memory is a high-density, low-cost, nonvolatile. read/write storage solution for a or 11.7V-12.3V. Its low voltage operation ,H28F320BJE-PTTL90 can operate at V,,=2.7V-3.6V and V,,,- -2.lV-3.6V apability realize battery life and suits for cellular phone application. is Boot, Parameter and Main-blocked architecture, low voltage and extended cycling provide for highly flexible component uitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal solution for code data storage applications. `or secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to )RAM, the LH28F320BJE-PTTL90 offers foui levels of protection: absolute protection with VCCW SHAR!= LJSF32JO2 -- 1 INTRODUCTION This datasheet contains LH28F320BJE-PI-l-L90 specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4 and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. A block erase operation erases one of the device's 32K word/64K-byte blocks typically within 1.2s (3V V,,. 3\ Vccw), 4K-word/8K-byte blocks typically within 0.6s (3\ V,,. 3V Vccw) independent of other blocks. Each block can be independently erased minimum 100.000 times Block erase suspend mode allows system software tc suspend block erase to read or write data from any other block. Writing memory data is performed in word/byu increments of the device's 32K-word blocks typically within 33~s (3V V,,. 3V V,,,), 6JK-byte block! typically within 31ps (3V V,,. 3V Vccw). 4K-wore blocks typically within 36~s (3V V,,. 3V Vccw). 8Kbyte blocks typically within 32~s (3V V,,. 3V Vccw). Word/byte write suspend mode enables the system to reac data or execute code from any other flash memory array location. 1.1 Features Key enhancements of LH28F320BJE-PTTL90 Flash memory are: *Single low voltage operation *Low power consumption *Enhanced Suspend Capabilities *Boot Block Architecture Please note following: boot block `I l VCCvtK has been lowered to l.OV to support 2.7V3.6V block erase, full chip erase, word/byte write and lock-bit configuration operations. The V,, voltage transitions to GND is recommended for designs that switch V,,, off during read operation. Individual block locking uses a combination of bits seventy-one block lock-bits, a permanent lock-bit ant WP# pin. to lock and unlock blocks. Block lock-bits gate block erase, full chip erase and word/byte write operations. while the permanent lock-bit gates block lockbit modification and locked block alternation. Lock-bil configuration operations (Set Block Lock-Bit, Set Permanent Lock-Bit and Clear Block Lock-Bits commands) set and cleared lock-bits. The status register indicates when the WSM's block erase. full chip erase, word/byte write or lock-bit configuration operation is finished. The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RYiBY# minimizes both CPU overhead and system power consumption. When low, RY/J3Y# indicates that the WSM is performing a block erase, full chip erase. word/byte write or lock-bit configuration. RY/BY#-high 2 indicates that the WSM is ready for a new command. block erase is suspended (and word/byte write is inactive), word/byte write is suspended, or the device is in reset mode. 1.2 Product Overview The LH28F320BJE-PTTL90 is a high-performance 32MIit Boot Block Flash memory organized as 2M-word of 16 )its or 4M-byte of 8 bits. The 2M-word/4M-byte of data is u-ranged in two 4K-word/8K-byte boot blocks, six 4Kvord/8K-byte parameter blocks and sixty-three 32Kvord/64K-byte main blocks which are individually :rasable, lockable and unlockable in-system. The memory nap is shown in Figure 3. The dedicated V ccw pin gives complete data protection vhen Vccw SHARP LHF32JO2 The access time is 90ns (tAvQv) over the operating temperature range (0C to +7O"C) and V, supply voltage range of 2.7V-36V. The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode. the typical I,-, current is 4pA (CMOS) at 3.OV V,,. When CE# and RP# pins are at V,,. the I,, CMOS standby mode is enabled. When the RP# pin is at GND, reset mode is enabled which minimizes power consumption and provides write protection. A reset time (tpHQv) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tpHEL) from RP#I-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. Please do not execute reprogramming "0" for the bit which has already been programed "0". Overwrite operation may generate unerasable bit. In case of reprogramming "0" to the data which has been programed "1". .Program "0" for the bit in which you want to change data from "1" to "0". .Program "1" for the bit which has already been programmed "0". For example, changing data from "10111101" "10111100" requires "11111110" programming. to 4 1.3 Product Description 1.3.1 Package Pinout LH28F320BJE-PTTL90 Boot Block Flash memory available in 48-lead TSOP package (see Figure 2). is 1 1.3.2 Block Organization This product features an asymmetrically-blocked architecture providing system memory integration. Each erase block can be erased independently of the others up to 100,000 times. For the address locations of the blocks, see the memory map in Figure 3. Boot Blocks: The boot block is intended to replace a dedicated boot PROM in a microprocessor or microcontroller-based system. This boot block 4K words (4,096words) features hardware controllable writeprotection to protect the crucial microprocessor boot code from accidental modification. The protection of the boot block is controlled using a combination of the V,,, RP#, WP# pins and block lock-bit. Parameter Blocks: The boot block architecture includes parameter blocks to facilitate storage of frequently update small parameters that would normally require an EEPROM. By using software techniques, the word-rewrite functionality of EEPROMs can be emulated. Each boot block component contains six parameter blocks of JK words (4.096 words) each. The protection of the parameter block is controlled using a combination of the Vccw, RP# and block lock-bit. Main Blocks: The reminder is divided into main blocks for data or code storage. Each 32M-bit device contains sixtythree 32K words (32.768 words) blocks. The protection of the main block is controlled using a combination of the Vccw. RP# and block lock-bit. Rev. 1.X -- LHF32JO2 5 r Figure I. Block Diagram Al5 Al4 43 Al? All 40 A `48 A19 ho Ez 0 2 3 6 1 4 5 48 I 47 I 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 Al6 BYTE# GND WE# RP# vccw WP# RY/BY# 48 A17 2 AS A4 A3 A? Al 8 9 10 11 12 13 1-l 15 16 17 1s 19 20 21 22 23 24 DQI~/AI DQ7 DQIJ DQs DQu W5 48-LEAD STANDARD TSOP PINOUT DQlz DQI 12mm x 20mm TOP VIEW vcc DQII DQ3 DQIO DQz. DQ9 DQI DQs DQo OE# GND Cl3 `%I Figure 2. TSOP &Lead Pinout Rev. 1.2 SHARP LHF32JO2 Table 1. Pin Descriptions Name and Function ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. A-t: Lower address input while BYTE# is V,,. A-, pin changes DQ, j pin while BYTE# is V,,. A, j-A20: Main Block Address. A,1-A20: Boot and Parameter Block Address. DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles: outputs data during memory array, status register and identifier code read cycles. Data pins float to highimpedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. DQ*-DQtj pins are not used while byte mode (BYTE#=V,). Then. DQtj pin changes A-, address input. CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. CE#-high deselectsthe device and reduces power consumption to standby levels. RESET: Resets the device internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provides data protection during power transitions. Exit from reset mode sets the device to read array mode. RP# must be V, during power-up. OUTPUT ENABLE: Gates the device's outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the risine edge of the WE# uulse WRITE PROTECT: When WP# is V,. boot blocks cannot be written or erased. When WP# is V,, locked boot blocks can not be written or erased. WP# is not affected parameter and main blocks. BYTE ENABLE: BYTE# V, places device in byte mode (x8). All data is then input or output on DQ,,. and DQs-, j float. BYTE# V,, places the device in word mode (x 16), and turns off the A-t input buffer. READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is performing an internal operation (block erase, full chip erase, word/byte write or lock-bit configuration). RY/BY#-high Z indicates that the WSM is ready for new commands. block erase is suspended. and word/byte write is inactive, word/byte write is suspended, or the device is in reset mode. BLOCK ERASE, FULL CHIP ERASE, WORD/BYTE WRITE OR LOCK-BIT CONFIGURATION POWER SUPPLY: For erasing array blocks. writing words/bytes or configuring lock-bits. With VCCWIVCCWLK. memory contents cannot be altered. Block erase, full chip erase. word/byte write and lock-bit configuration with an invalid Vccw (see 6.2.3 DC Characteristics) produce spurious results and should not be attempted. Applying 12V+O.3V to Vccw during erase/write can only be done for a maximum of 1000 cycles on each block. Vccw may be connected to 12V&.3V for a total of 80 hours maximum. DEVICE POWER SUPPLY: Do not float any power pins. With V,,IV,,,, all write attempts to the flash memory are inhibited. Device operations at invalid V,, voltage (see 6.2.3 DC Characteristics) produce spurious results and should not be attempted. GROUND: Do not float any ground pins. Symbol TYW INPUT A-1 A,-*20 1 DQ,-DQ,, INPUT/ OUTPUT CE# RP# OE# WE# WI% INPUT INPUT INPUT INPUT INPUT BYl-E# INPUT OPEN DRAIN OUTPUT RY/BY# Vccw SUPPLY vcc GND SUPPLY SUPPLY Rev. 1.25 SHARP LHF32J02 7 -- r r Top Boot L%(rA( EFlTF iffooo IFEFFF II-E@Xl IFDFFF IFWOO IFCFFF IFCWO IFBFFF IFBCQO IFAFFF IFAOOO ll?xFF 1F9m IFSFFF lF8lXKJ lF7tFF 1's IEBMX) lE7Ftl= IEOWO lDFFFl= lD8KlC lD7FFF IWO00 ICFFFF Ic8cixl IUFFF ICWOO IBFFFF IWOW lB7FFF IBoo IAHFF IA8000 lA7FFF IALXXIO 19FFFF l98cm 197FFF 190ooO 18FFFF 188cco 187FFF 18OooO 17FFFF 178000 177FFF 17ocQO 16tTFF l68ONl 167lTF 16OGQO 15FFFF lS8CCil IVFFF l5Oca I.R=FF I J8000 IUFFF IUHXW) IWFFF 138OW 137m 13OcQo 12FFFF I28000 117FFF IIOIXH I I I-TFT 118000 117tTF I IOocdI I 0twF 108ooO 107tFF ICWXX) JKWIXKB Boot Block _1. ?FDFFF L"W `FCOOO 3FBm :r&E 3F8Mnl 3F7FFF 3F6000 3FSFFF 3MMX) 3F3FFF 3F1000 3FlFW 3FOiXMl 3EFFFF 3EOooO 3DFFFF 3wOQO 3cFFFF 3cmo 3BFFFF 3BCWO 3AFFFF 3AOCHl 39FFFF 390000 38FFFF 3scml 37FFFF 37oOm 36FFFF 36OMM 35FFFF 35OMx) 3aT-FF ?10000 33FFFF 330000 32tTF-F 310000 3lFFFF 31ooOQ 3oFFFF 3cQOm ?FFFFF 2FOOOO EFFFF lEOOO0 ?DlTFF JDCCCiI 2CFFFF ?CoooO 2BFtFF ?BooOO MFFFF 2A0000 ?9FFFF 19om XWFFF 28OCUl YFFFF ?7ccm 36FFFF 26OWX 25FFFF 250000 24=FFF 140000 I3FmF 230000 2ZFFFF 22oooo 1llTFF 210000 lOFFFF 30Ofl00 ho-A01 [AGO-A-II OEFWF OEOQCO ODFFFF OCOCOO OBFFFF OBOIMO OAFFFF n . nnnn 32KW/64KB 33KW/h-LKB 32KW/64KB 3?KW/h4KB Mam Main Main Main Block Block Block Block 59 60 61 62 `I ::g I ;;;z OIFFFF 1 0 I two CQmtT; imoo Figure 3. Memory Map Rev. I.25 SHARI= LHF32JO2 2 PRINCIPLES OF OPERATION The LH28F320BIEPTTL90 Flash memory includes an on-chip WSIM to manage block erase, full chip erase, word/byte write and lock-bit configuration functions. It allows for: fixed power supplies during block erase. full chip erase, word/byte write and lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from reset mode (see section 3 Bus Operations). the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the V,, voltage. High voltage on V,, enables successful block erase, full chip erase, word/byte write and lock-bit configurations. All functions associated with altering memory contents-block erase, full chip erase, word/byte write. lock-bit zonfigurationt status and identifier codes-are accessed via he CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, full chip erase, word/byte write and lock-bit configuration. The internal Algorithms are regulated by the WSM. including pulse .epetition, internal verification and margining of data. iddresses and data are internally latched during write :ycles. Writing the appropriate command outputs array lata, accesses the identifier codes or outputs status register iata. -- 8 Interface software that initiates and polls progress of block erase, full chip erase, word/byte write and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspend. Word/byte write suspend allows system software to suspend a word/byte write to read data from any other flash memory array location. 2.1 Data Protection memory contents cannot be When V,&VccwLK. altered. The CUI, with two-step block erase, full chip erase, word/byte write or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to Vccw. All write functions are disabled when V,, is below the write lockout voltage V,,, or when RP# is at V,. The device's block locking capability provides additional protection from inadvertent code or data alteration by gating block erase. full chip erase and word/byte write operations. Refer to Table 5 for write protection alternatives. Rev. 1.25 SHARI= LHF32JO2 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. -- 9 3.4 Reset RP# at V,, initiates the reset mode. In read modes: RP#-low deselects the memory. places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 1OOns. Time tpHQv is required after return from reset mode until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase. full chip erase. word/byte write or lock-bit configuration modes. RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tpBwL is required after RP# goes to logic-high (V,,) before another command can be written. As with any automated device. it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase. full chip erase, word/byte write or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset. proper CPU initialization may not occur because the flash memory may be providing status information instead of assay data. SHARP's flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 3.; Read Information can be read from any block, identifier codes or status register independent of the Vccw voltage. RP# can be at V,. The first task is to write the appropriate read mode command (Read Array. Read Identifier Codes or Read Status Register) to the CUI. Upon initial device power-up or after exit from reset mode. the device automatically resets to read array mode. Six control pins dictate the data flow in and out of the component: CE#, OE#, BYTE#, WE#, RP# and WP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control. and when active enables the selected memory device. OE# is the data output (DQo-DQ,,) control and when active drives the selected memory data onto the I/O bus. BYTE# is the device I/O interface mde control. WE# must be at V,,, RP# must be at V,,. and BYTE# and WP# must be at V, or V,,. Figure 16. 17 illustrates read cycle. 3.2 Output Disable With OE# at a logic-high level (V,,). the device outputs Ire disabled. Output pins (DQ,-DQ,j) are placed in a ligh-impedance state. 3.3 Standby C1E# at a logic-high level (V,,) places the device in standby mode which substantially reduces device power :onsumption. DQ,-DQ,, outputs are placed in a highmpedance state independent of OE#. If deselected during )lock erase. full chip erase. word/byte write or lock-bit :onfiguration, the device continues functioning, and :onsuming active power until the operation completes. Rev. 1.15 SHARP LHF32JO2 .5 Read Identifier Codes he read identifier codes operation outputs the manufacturer code. device code. block lock configuration Ides for each block and the permanent lock configuration )de (see Figure 4). Using the manufacturer and device Ides, the system CPU can automatically match the device ith its proper algorithms. The block lock and permanent mck configuration codes identify locked and unlocked ocks and permanent lock-bit setting. Top Boa 3FFFFF 3FEOO6 3FEOO5 3FEoo.t 3FEcm3 3FEOOO 3FDFFF 3FCCQ6 3FCOO5 3FCOO.t 3FCCO3 3FCMH) 3FBFFF 3FACC-5 3FAOO5 3FAOO.l 3FAOO3 3FACNM IFCFFF; IF9000 i ; 3F9FFF -- 10 3.6 OTP(One Time Program) Block The OTP block is a special block that can not be erased. The block is divided into two parts. One is a factory program area where a unique number can be written according to customer requirements in SHARP factory. This factory program area is "READ ONLY" (Already locked). The other is a customer program area that can be used by customers. This customer program area can be locked. After locking, this customer program area is protected permanently. The OTP block is read in Configuration Read Mode by writing Read Identifier Codes command(90H). To return to Read Array Mode, write Read Array command(FFH). The OTP block is programmed by writing OTP Program command(COH). First write OTP Program command and then write data with address to the device (See Figure 5). If OTP program is failed, SR.J(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR.I(DEVICE PROTECT STATUS) bit is set to "1" too. The OTP block is also locked by writing OTP Program command(COH). First write OTP Program command and then write data "FFFDH" with address "80H" to the device. Address "80H" of OTP block is OTP lock information. Bit 0 of address "80H" means factory program area lock status("1" is "NOT LOCKED". "0" is "LOCKED"). Bit 1 of address "SOH" means customer program area lock status. The OTP lock information can not be cleared, after once it is set. (Parameter Reserved Parameter Blocks 1 through 4) ; 3F1000 3FIFFF for Future Implementation Code 3FMW6 3FooOS 3FOOOJ 3FOOO3 3FoooO 3EFFFF 3E0006 3EOOo5 3EOOOJ 3EOCO3 3EMXW) i 3DFFFF 1 oooO85 1 Block 5 Lock Confieumtion ooom OOIFFF Customer Program Area ~~__~_~^~~~~~-~l~----~---------~~- IFOWl IFOiXQ IEFFFF 008000 j i Reserved (Man Reserved for Future Implementr&ion Main Block 0, Blocks forFuture 1 throyh 61) 1 OOOIOA j Implementation Customer Factory Program Program Area Lock Area Lock 000080 1 Figure 5. OTP Block Address Map Figure 4. Device Identifier Code Memory Map Rev. 1.35 SHARP LHF32JO2 11 -- 3.7 Write Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When V,,=2.7V-3.6V and the CUI additionally controls block VCCW=VCCWH1/2~ erase, full chip erase, word/byte write and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Full Chip Erase command requires appropriate command data and an address within the device. The Word/Byte Write command requires the command and address of the location to be written. Set Permanent and Block Lock-Bit commands require the command and address within the device (Permanent Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Figures 18 and 19 illustrate WE# and CE# controlled write operations. 4 COMMAND DEFINITIONS When the V,, voltage IVCCWLK. Read operations from the status register, identifier codes. or blocks are enabled. enables successful block Placing VccWH1i2 on VCCW erase. full chip erase. word/byte write and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands. Table 2.1. Bus Operations (BYTEI Read Identifier Codes X Write X X 673 DIN VI, VI, VI, VIL NOTES: memory contents can be read. but not altered. 1. Refer to DC Characteristics. When VccwlVccwLK. 2. X can be V, or V,, for control pins and addresses, and VcCWLK or VCCWH,,2 for V,,,. See DC Characteristics for VCCWLK voltages. 3. RY/BY# is V,, when the WSM is executing internal block erase, full chip erase, word/byte write or lock-bit configuration algorithms. It is High Z during when the WSM is not busy, in block erase suspend mode (with word/byte write inactive). word/byte write suspend mode or reset mode. 4. RP# at GND-cO.2V ensures the lowest power consumption. 5. See Section 4.2 for read identifier code data. 6. Command writes involving block erase, full chip erase, word/byte write or lock-bit configuration are reliably executed when V ccw=VccwHt/q and Vcc=2.7V-3.6V. 7. Refer to Table 3 for vahd D,, during a write operation, 8. Never hold OE# low and WE# low at the same timing. Rev. 1.25 -- LHF32JO2 12 Table 3. Command Definition&lo) Full Chip Erase 2 1 Write 1 5.6 1 I I X x X ,X X X X X 1 30H 1 Write I Write 1 I X WA ) / DOH WD II Word/Byte Write I 2 1 Write Write Write Write Write Write Write ) 4yy~ BOH DOH 60H 60H 60H COH I I/ Block Erase and Word/Byte Write Suspend Block Erase and Word/Byte Write Resume Set Block Lock-Bit Clear Block Lock-Bits Set Permanent Lock-Bit OTP Program 1 1 2 2 2 2 > .j 5 8 7.8 9 Write Write Write Write BA X X OA OlH DOH FIH OD 1. BUS operations are defined in Table 2.1 and Table 2.2. 2. X=Any valid address within the device. IA=Identifier Code Address: see Figure 4. BA=Address within the block being erased. WA=Address of memory location to be written. OA=Address of OTP block to be written: see Figure 5. 3. ID=Data read from identifier codes. SRD=Data read from status register. See Table 6 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). OD=Data to be written at location OA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). 4. Following the Read Identifier Codes command. read operations access manufacturer, device. block lock configuration and permanent lock configuration codes. See Section 4.2 for read identifier code data. 5. If WP# is V,, boot blocks are locked without block lock-bits state. If WP# is Vt,, boot blocks are locked by block lockbits. The parameter and main blocks are locked by block lock-bits without WP# state. 6. Either 4OH or 10H are recognized by the WSM as the word/byte write setup. 7. The clear block lock-bits operation simultaneously clears all block lock-bits. 8. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands can not be done. 9. Once the permanent lock-bit is set. permanent lock-bit reset is unable. 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. Rev. 1.25 SHARP LHF32JO2 4.3 Read Status Register Command The status register may be read to determine when a block erase, full chip erase, word/byte write or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the Vccw voltage. RP# can be VII-t. 4.1 Read Array Command Upon initial device power-up and after exit from reset mode. the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, full chip erase. word/byte write or lock-bit configuration the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Word/Byte Write Suspend command. The Read Array command functions independently of the Vccw voltage and RP# can be V,,. 4.2 Read Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 4 retrieve the manufacturer, device. block lock configuration and permanent lock configuration codes (see Table 4 for Identifier code values). To terminate the operation. write another valid command. Like the Read Array command, he Read Identifier Codes command functions ndependently of the V,-w voltage and RP# can be V,,. `allowing the Read Identifier Codes command, the `allowing information can be read: Table 4. Identifier Codes Address(`) Code Manufacture Code Device Code Block Lock Configuration *Block is Unlocked *Block is Locked *Reserved for Future Use Permanent Lock Configuration Data(3) 4.4 Clear Status Register Command Status register bits SR.5. SR.4. SR.3 or SR.l are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 6). By allowing system software to reset these bits. several operations (such as cumulatively erasing multiple blocks or writing several words/bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register. the Clear Status Register command (50H) is written. It functions independently of the applied Vccw Voltage. RP# can be V,,. This command is not functional during block erase or word/byte write suspend modes. [A,,-A,1 PQ,-DQ,l OOOOOH BOH OOOOlH E2H B A( I,+2 `~~~~~~~ ., ,. .,... DQ,=O DQ,= 1 BA selects the specific block lock configuration code to be read. See Figure 4 for the device identifier code memory map. !. A-, don't care in byte mode. 1. DQtj-DQ9 outputs OOH in word mode. _I Rev. 1.25 SHARP LHF32JO2 4.5 Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFFFH/FFH). Block preconditioning. erase. and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 6). The CPU can detect block erase completion by analyzin_g the output data of the RY/BY# pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also. reliable block erasure can only occur when Vcc=2.7V-3.6V and VCCW=VCCwH1,?. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VCCWIVCCWLK. SR.3 and SR.5 will be set to "1". Successful block erase requires for boot blocks that WP# is V,, and the corresponding block lock-bit be cleared. In parameter and main blocks case, it must be cleard the corresponding block lock-bit. If block erase is attempted when the excepting above conditions. SR.1 and SR.5 will be set to "1". status register mode until a new command is issued. I error is detected on a block during full chip erase operation. WSIM stops erasing. Full chip erase operatior start from lower address block. finish the higher addres! block. Full chip erase can not be suspended. This two-step command sequence of set-up followed b) execution ensures that block contents are not accidentall) erased. An invalid Full Chip Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable full chip erasure can only OCCUI In the when V,,- -2 7V-3.6V and VCCw=VCCWHln. absence of this high voltage. block contents are protectec against erasure. If full chip erase is attempted while V CCWIVCCwrK. SR.3 and SR.5 will be set to "1" Successful full chip erase requires for boot blocks thal WP# is V,, and the corresponding block lock-bit be cleared. In parameter and main blocks case, it must be cleard the corresponding block lock-bit. If all blocks are locked. SR.1 and SR.5 will be set to "1". 4.7 Word/Byte Write Command Word/Byte write is executed by a two-cycle command sequence. Word/Byte write setup (standard 40H 01 alternate 10H) is written. followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the word/byte write and write verify algorithms internally. After the word/byte write sequence is written, the device automatically outputs status resister data when read (see Figure 8). The CPU can detect the completion of the word/byte write event by analyzing the RY/BY# pin OI status register bit SR.7. When word/byte write is complete, status register bit SR.J should be checked. If word/byte write error is detected. the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. Reliable word/byte writes can only occur when V,,=2.7V-3.6V and VCCw=VCCWHIR. In the absence of this high voltage. memory contents are protected against word/byte writes. If word/byte write is attempted while VCCW I'his command followed by a confirm command erases all af the unlocked blocks. A full chip erase setup (30H) is !irst written. followed by a full chip erase confirm (DOH). 4fter a confirm command is written. device erases the all mlocked blocks block by block. This command sequence .equires appropriate sequencing. Block preconditioning. :rase and verify are handled internally by the WSIM invisible to the system). After the two-cycle full chip :rase sequence is written. the device automatically outputs status register data when read (see Figure 7). The CPU can ietect full chip erase completion by analyzing the output lata of the RY/BY# pin or status register bit SR.7. Nhen the full chip erase is complete. status register bit lR.5 should be checked. If erase error is detected. the tatus register should be cleared before system software ittempts corrective actions. The CUI remains in read Rev. 1.25 SHAi?l= LHF32JO2 1.5 4.8 Block Erase Suspend Command 4.9 Word/Byte Write Suspend Command The Block Erase Suspend command allows block-erase interruption to read or word/byte write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to High Z. Specification twHRz2 defines the block erase suspend latency. When Block Erase Suspend command write to the CUI, if block erase was finished. the device places read array mode. Therefore, after Block Erase Suspend command write to the CUI, Read Status Register command (70H) has to write to GUI, then status register bit SR.6 should be checked for places the device in suspend mode. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Word/Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Word/Byte Write Suspend command (see Section 4.9), a word/byte write operation can also be suspended. During a word/byte write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/BY# output will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status. I'he only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written :o the flash memory, the WSM will continue the block xase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to VOL. After he Erase Resume command is written, the device automatically outputs status register data when read (see 3gure 9). V,,, must remain at V,,,,,* (the same Vrccw level used for block erase) while block erase is uspended. RP# must also remain at V,,. WP# must also ,emain at V,, or V,, (the same WP# level used for block :rase). Block erase cannot resume until word/byte write operations initiated during block erase suspend have :ompleted. f the period of from Block Erase Resume command write the CUI till Block Erase Suspend command write to the 3JI be short and done again and again, erase time be xolonged. The Word/Byte Write Suspend command allows word/byte write interruption to read data in other flash memory locations. Once the word/byte write process starts, writing the Word/Byte Write Suspend command requests that the WSM suspend the Word/Byte write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Word/Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the word/byte write operation has been suspended (both will be set to "1"). RY/BY# will also transition to High Z. Specification tWHRZ1 defines the word/byte write suspend latency. When Word/Byte Write Suspend command write to the CUI, if word/byte write was finished. the device places read array mode. Therefore. after Word/Byte Write Suspend command write to the CUI, Read Status Register command (70H) has to write to CUI, then status register bit SR.2 should be checked for places the device in suspend mode. At this point, a Read Array command can be written to read data f$om locations other than that which is suspended. The only other valid commands while word/byte write is suspended are Read Status Register and Word/Byte Write Resume. After Word/Byte Write Resume command is written to the flash memory, the WSM will continue the word/byte write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to V,,. After the Word/Byte Write Resume command is written, the device automatically outputs status register data when read (see Figure 10). Vccw must remain at VCCWHIz (the same V,, level used for word/byte write) while in word/byte write suspend mode. RP# must also remain at V,. WP# must also remain at V,, or V,, (the same WP# level used for word/byte write). If the period of from Word/Byte Write Resume command write to the GUI till Word/Byte Write Suspend command write to the CUI be short and done again and again. write time be prolonged. o Rev. I .`75 SHARP LHF32JO2 4.10 Set Block and Permanent Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits. a permanent lock-bit and WP# pin. The block lock-bits and WP# pin gates program and erase operations while the permanent lock-bit gates block-lock bit modification. With the permanent lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Permanent Lock-Bit command, sets the permanent lock-bit. After the permanent lock-bit is set, block lock-bits and locked block contents cannot altered. See Table 5 for a summary of hardware and software write protection options. Set block lock-bit and permanent lock-bit are executed by a two-cycle command sequence. The set block or permanent lock-bit setup along with appropriate block or device address is written followed by either the set block Lock-bit confirm (and an address within the block to be .ocked) or the set permanent lock-bit confirm (and any levice address). The WSM then controls the set lock-bit rlgorithm. After the sequence is written. the device mtomatically outputs status register data when read (see ?gure 11). The CPU can detect the completion of the set ock-bit event by analyzing the RY/BY# pin output or ;tatus register bit SR.7. When the set lock-bit operation is complete. status register Iit SR.3 should be checked. If an error is detected, the `tatus register should be cleared. The GUI will remain in ead status register mode until a new command is issued. this two-step sequence of set-up followed by execution fnsures that lock-bits are not accidentally set. An invalid ;et Block or Permanent Lock-Bit command will result in tatus register bits SR.4 and SR.5 being set to "1". Also, eliable operations occur only when Vcc=2.7V-3.6V and I CCW=vCCWH1/2~ In the absence of this high voltage, lck-bit contents are protected against alteration. L successful set block lock-bit operation requires that the ermanent lock-bit be cleared. If it is attempted with the ermanent lock-bit set, SR.1 and SR.4 will be set to "1" nd the operation will fail. 4.11 Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the permanent lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the permanent lock-bit is set, block lock-bits cannot cleared. See Table 5 for a summary of hardware and software write protection options. Clear block lock-bits operation is executed by a two-cycle command sequence. A clear block lock-bits setup is first written. After the command is written. the device automatically outputs status register data when read (see Figure 12). The CPU can detect completion of the clear block lock-bits event by analyzing the RY/BY# Pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur when V,-=2.7V-3.6V and VCCw=VCCwH1,2. If a clear block iock-bits operation is attempted while Vc+V,,,,, SR.3 and SR.5 will be set to "1". In the absence of this high voltage. the block lock-bits content are protected against alteration. A successful clear block lock-bits operation requires that the permanent lock-bit is not set. If it is attempted with the permanent lock-bit set, SR.1 and SR.5 will be set to "1" and the operation will fail. If a clear block lock-bits operation is aborted due to Vccw or Vcc transitioning out of valid range or RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. Once the permanent lock-bit is set. it cannot be cleared. Rev. 1.25 SHARP LHF32JO2 4.12 OTP Program Command programs. If OTP program is attempted whik Vccw5Vt--,,. status register bits SR.3 and SR.4 is se to "1". If OTP write is attempted when the OTP Lock-bi is set, SR.l and SR.4 is set to "1". 1 3TP program is executed by a two-cycle command sequence. OTP program command(COH) is written, 1rollowed by a second write cycle that specifies the address i md data (latched on the rising edge of WE#). The WSM t hen takes over, controlling the OTP program and program \ verify algorithms internally. After the OTP program C :ommand sequence is completed, the device automatically tutputs status register data when read (see Figure 13). The ; ZPU can detect the completion of the OTP program by 2analyzing the output data of the RY/BY# pin or status I egister bit SR.7. ( I 4.13 Block Locking by the WP# This Boot Block Flash memory architecture features twc hardware-lockable boot blocks so that the kernel code foi the system can be kept secure while other blocks arc programmed or erased as necessary. The lockable two boot blocks are locked when WP#=V,, any program or erase operation to a locked `block will result in an error, which will be reflected in the status register. For top configuration, the top two boot blocks are lockable. For the bottom configuration, the bottom twc boot blocks are lockable. If WP# is V, and block lock. bit is not set, boot block can be programmed or erased normally (Unless V,, is below VCCwtK). WP# is valid only two boot blocks, other blocks are not affected. Nhen OTP program is completed, status register bit SR.4 hould be checked. If OTP program error is detected, the Status register should be cleared. The internal WSM verify Conly detects errors for "1"s that do not successfully F brogram to "0"s. The CUI remains in read status register n node until it receives other commands. \ s F leliable OTP program can be executed only when \ I,,=2.7V-3.6V and VCCw=VCCWHln. In the absence of tlhis voltage, memory contents are protected against OTP Table 5. Write Protection Alternatives Rev. 1.26 SHARI= LHF32JO2 Table 6. Status Register Definition 1 WBWSLBS 1 VCCWS 1 WBWSS 4 3 .2 NOTES: SR.7 = WRITE STATE iMACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR BLOCK L&X-BITS STATUS (ECBLBS) 1 = Error in Block Erase, Full Chip Erase or Clear Block Lock-Bits 0 = Successful Block Erase. Full Chip Erase or Clear Block Lock-Bits SR.4 = WORD/BYTE WRITE AND SET LOCK-BIT STATUS (WBWSLBS) 1 = Error in Word/Byte Write or Set Block/Permanent Lock-Bit 0 = Successful Word/Byte Write or Set Block/Permanent Lock-Bit SR.3 = Vccw STATUS (VCCWS) 1 = Vccw Low Detect, Operation Abort 0 = Vccw OK SR.2 = WORD/BYTE WRITE SUSPEND STATUS (WBWSS) 1 = Word/Byte Write Suspended 0 = Word/Byte Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Block Lock-Bit, Permanent Lock-Bit and/or WP# Lock Detected, Operation Abort 0 = Unlock GR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) If both SR.5 and SR.4 are "1"s after a block erase. full chip erase or lock-bit configuration attempt. an improper command sequence was entered. Check RY/BY# or SR.7 to determine block erase. full chip erase, word/byte write or lock-bit configuration completion. SR.6-0 are invalid while SR.7="0". 18 WSMS 7 1 BESS 6 1 ECBLBS 5 1 DPS 1 R 0 1 SR.3 does not provide a continuous indication of V,-cw level. The WSM interrogates and indicates the V,--w level only after Block Erase. Full Chip Erase, Word/Byte Write or Lock-Bit Configuration command sequences. SR.3 is not guaranteed to reports accurate feedback only when VCCW'VCCWHl12. SR.1 does not provide a continuous indication of permanent and block lock-bit and WP# values. The WSM interrogates the permanent lock-bit, block lock-bit and WP# only after Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration command sequences. It informs the system. depending on the attempted operation, if the block lock-bit is set, permanent lock-bit is set and/or WP# is V,,. Reading the block lock and permanent lock configuration codes after writing the Read Identifier Codes command indicates permanent and block lock-bit status. SR.0. is reserved for future use and should be masked out when polling the status resister. Rev. 1.25 SHARI= LHF32JO2 19 r SLan BU, opryiom Command Comments Dam=7OH Wrne 70H .: Add-X (heck SR.7 Sldhy I=WSM Ready O=WSM Buy Dao=?OH Ad&X W"te Emc Setup Wme ?OH I + Wnle WH. Block Address Full Sfam.s Check if Desired FULL. STATL'S CHECK PROCEDL'RE BUS ops!uon Command I Cmlme"u Standby Check SR.3 I=Vccw Erra D&Cl Check SR.5 I=Block Erase Enc. Comm.nd Sqwnce Block Ervs Error Figure 6. Automated Block Erase Flowchart , Rev. 1.X LHF32JO2 20 (7) v wrm rnH + Read Stmus Wnre 30H L I Wnle DOH Red Skws Rcg,ster SR.7= 9 I Full Status Check ,f Dared 0 Full status check can be done af,er each lid1 chip erase. Write FFH after the bet oprauon 80 place Lnca in rend array mode. -r-' Full Ch,p Erase Complete FL'LL STATUS CHECK PROCEDURE BUS opmuoo Read %m. Regnter Daw(Sce Above) Command COmlllCdS Standby Check SR.3 I=Vccw Erra Detect Check SR.1 ,=Dcv,cr Pra*ct DrteEt (All Bloclu are laked) Staodby Device Raea Error Standby cheek SR.4.S Bad, I=Command S,quence Error Standby comrmnd Scqwnce Cheek SR.5 I&d, Cb,p Erase Error in wer SR.5. SR.4. SR.3 nml SR.1 are only cleared by Ihe Clcu Suws Rsg~sr Command where muhiplc blc&s are erased before full ~tatu.sis checked. If ci-rcs IS detected. clear ,hc Status Regster before a"emptw reU,`or ahcr error recovery. Full Oup G-se Error Full Ch,p Gus S"cc<,rf"l Figure 7. Automated Full Chip Erase Flowchart Rev. 1.25 SHARP LHF32JO2 r Read Swus Rtgstcr SR.7= I 0 Write 4OH OT IOH g wnu WordKlgrc Data and Ad&w .; Full Status Check d &sued y%& FULL STATL'S CHECK PROCEDDRE WordlBjw Wrnz Succzssiul Figure 8. Automated Word/Byte Write Flowchart Rev. 1.25 SHARI= LHF32JO2 22 -- WWC ErAYe Suspend Data=BOH Addr=X Sollu Addr=X Regmer Data had Wnlz Bbck Emu Completed Erase ReSUiV Da=DOH Addr=X Figure 9. Block Erase Suspend/Resume Flowchart Rev. 1.25 SHARP LHF32JO2 23 -- Command Commrnta W"lC Dam=DOH Ad&X Figure 10. Word/Byte Write Suspend/Resume Flowchart Rev. 1.25 SHARt= LHF32JO2 24 -- BUS operaron Command I Das70H Addr=X Cornmenu Read Swtw Reg,rts Data Standby Check SR.7 I=WSM Ready G=WSM Bury Dam=.ZQH AddzX DatsOIH~Blwk). BlocWDence Address FL'LL STATL'S CHECK PROCEDCRE BUS operauoa Command I Cheek SR.3 Standby l=VccH. Ena Detect Cheek SR. 1 I=Dwlcc RaeLZ DelCd Pe,,,w,en, Lock-B,1 II Scr (SC, Bluk Lock-B,1 Opxrauoa) Chsck SR.J.5 Bolh I=Cammnnd Sequence Enor Command Scqwnce Set Lock-BtI Error Figure 11. Set Block and Permanent Lock-Bit Flowchart -I Rev. 1.25 -- LHF32JO2 25 r Comments Wnta Dam=70H Addr=X Read SU.IU Regstrr Data Check SR.7 Standby I=WSM Ready QWSM Busy FULL STATLS CHECK PROCEDL'RE Bus OperJuon Rend Status Re$,ner am&Y Above, Command I cheek SR.3 ,cV~~ Erra Dcrzct stmdby Device Raea Error Command Sequence "car Block Leek-Bm Rev. 1.25 -- LHF32JO2 26 r BUS openuo. Command Cornmenu Check SR.7 Standby I=WSM Ready QWSM setup OTP Rogml Ds,=COH Ad&X Buy FLU STAT-L'S CHECK PROCEDL'RE Standby Standby Cbcck SR.1 I=Dcrice Raect Deted Figure 13. Automated OTP Program Flowchart Rev. 1.25 SHARP LHF32JO2 5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. 27 5.3 Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a O.lpF ceramic capacitor connected between its V,, and GND and between its V,,, and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally. for every eight devices. a 4.7pF electrolytic capacitor should be placed at the array's power supply connection between V,, and GND. The bulk capacitor will overcome volta_pe slumps caused by PC board trace inductance. 5.4 VCCW Trace on Printed Circuit Boards Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the Vccw Power supply trace. The Vccw pin supplies the memory cell current for word/byte writing and block erasing. Use similar trace widths and layout considerations given to the V,, power bus. Adequate V ccw supply traces and decoupling will decrease Vccw voltage spikes and overshoots. 5.2 RY/BY# and WSM Polling RY/BY# is an open drain output that should be connected to V,, by a pull up resistor to provides a hardware method of detecting block erase. full chip erase. word/byte write and lock-bit configuration completion. It transitions low after block erase, full chip erase. word/byte write or lockbit configuration commands and returns to V,, (while RY/BY# is pull up) when the WSM has finished executing the internal algorithm. RY/BY# can be connected to an interrupt input of the system CPU or controller. It is active at all times. RY/BY# is also High Z when the device is in block erase suspend (with word/byte write inactive), word/byte write suspend 3r reset modes. 5.5 Vcc, VCCW, RP# Transitions Block erase, full chip erase,.word/byte write and lock-bit configuration are not guaranteed if V,-, falls outside of a valid VCCWH1,7, range. V,, falls outside of a valid 2.7V3.6V range, or RP##Vm. If V,,-w error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5. depending on the attempted operation. If RP# transitions to V, during block erase, full chip erase. word/byte write or lock-bit configuration. RY/BY# will remain low until the reset operation is complete. Then. the operation will abort and the device will enter reset mode. The aborted operation may leave data partially altered. Therefore. the command sequence must be repeated after normal operation is restored. Device power-off or RP# transitions to V,, clear the status register. The GUI latches commands issued by system software and is not altered by Vccw or CE# transitions or WSM actions. Its state is read array mode upon power-up. after exit from reset mode or after V,, transitions below V,,,. Rev. 1.25 SHARP LHF32JO2 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block erase, full chip erase, word/byte write or lock-bit configuration during power transitions. Upon power-up, the device is indifferent as to which power Supply (Vccw or V,,) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for V,, voltages above VLKO when Vccw is active. Since both WE# and CE# must be low for a command write, driving either to V,, will inhibit writes. The CUPS twostep command sequence architecture prov.ides added level Df protection against data alteration. c In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled while RP#=V, regardless of its control inputs state.' 28 5.8 Data Protection Method Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto WE# signal or power supply. may be interpreted as false commands, causing undesired memory updating. To protect the data stored in the flash memory against unwanted overwriting. systems operating with the flash memory should have the following write protect designs. as appropriate: 1) Protecting data in specific block When a lock bit is set. the corresponding block (includes the 2 boot blocks) is protected against overwriting. By setting a WP# to low. only the 2 boot blocks can be protected against overwriting. By using this feature, the flash memory space can be divided into the program section (locked section) and data section (unlocked section). The permanent lock bit can be used to prevent false block bit setting. For further information on setting/resetting lock-bit. refer to the specification. (See chapter 4.10 and 4.11.) 2) Data protection through Vccw When the level of V,-,, is lower than VCC,vrK (lockout voltage), write operation on the flash memory is disabled. All blocks are locked and the data in the blocks are completely write protected. For the lockout voltage. refer to the specification. (See chapter 6.2.3.) 3) Data protection through RP# When the RP# is kept low during read mode. the flash memory will be deep-power-down mode. then write protecting all blocks. When the RF% is kept low during power up and power down sequence such as voltage transition. write operation on the flash memory is disabled. write protecting all blocks. For the details of RP# control. refer to the specification. (See chapter 5.6 and 6.2.7.) 5.7 Power Dissipation When designing portable systems. designers must consider lattery power consumption not only during device operation, but also for data retention during system idle ime. Flash memory's nonvolatility increases usable Iattery life because data is retained when system power is .emoved. Rev. 1.25 SHARP LHF32JO2 29 6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature . During Read, Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration ...... ........ .. 0C to +7O"C(r) Storage Temperature During under Bias . ..... ..... .. ........ ........ .. -10C to +8O"C During non Bias ...... ... ....... .......... ...... -65C to +125"C Voltage On Any Pin (except V,, and V,,) ..... ...... -0SV to Vcc+0.5V(2) *WARNING: Stressing the device beyond the `Absolute Maximum Ratings" ma? cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended e.xposure beyond the "Operating Conditions" may affect device reliability. NOTES: V,, Supply Voltage .... ..... ... .._................. -0.2V to +4.6Vc2) Vccw Supply Voltage.. ....................... -0.2V to +13.0V(2y3) Output Short Circuit Current.. .............................. 100mAc4) I. Operating temperatureis for commercialtemperature product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on Vcc and Vccw pins. During transitions, this level may undershoot -2.OV for periods<20ns. to Maximum DC voltage on input/output pins are V,,+O.5V which, during transitions.may overshootto Vcc+2.0V for periods<20ns. 3. Maximum DC voltage on Vccw may overshoot to +13.OV for periods <20ns. Applying 12VkO.3V to V,,, during erase/write can only be done for a maximum of 1000cycleson eachblock. V,,, may be connected to 12V&3V for a total of 80 hours maximum. 4. Output shortedfor no more than one second.No more than one output shortedat a time. 5.2 Operating Conditions Symbol TA Vcc Temperature Vcc Operating Conditions and Parameter Min. Max. Unit OperatingTemperature 0 +70 "C V,, Supply Voltage (2.7V-3.6V) 2.7 3.6 V Test Condition .AmbientTemperature 5.2.1 CAPACITANCE(l) . Sampled,not 100%tested. Rev. 1.25 SHARP LHF32JO2 i.2.2 AC INPUT/OUTPUT TEST CONDITIONS 30 -- . ~-YqL=z~~T AC test inputs are driven at 2.7V for a Logic "1" and O.OV for aLogic Input rise and fall times (107~ to 90%) ~10 ns. "0". Input riming begins, and output timing ends, at 1.35V. Figure 14. Transient Input/Output Reference Waveform for Vcc=2.7V-3.6V Test Configuration Capacitance Loading Value Test Configuration C,(pF) V,,=2.7V-3.6V 50 DEVICE UNDER TEST CL Includes Jig Capacitance z - 0 - OUT CL Figure 15. Transient Equivalent Testing Load Circuit Rev. 1.25 SHARI= LHJ532JO2 6.2.3 DC CHARACTERISTICS DC Characteristics 1 V,,=2.7V-3.6V Notes Ma. TYP. 1 20.5 1 193 4 kO.5 20 1 Unit PA ClA r-IA V,,=V,,Max. CE#=RP#=Vr&.2V Test Conditions V,,=V,cMax. V,,=V,, or GND Sym. 1, IL0 Parameter Input Load Current Output Leakage Current V,, Standby Current Vcc Auto Power-Save Current kcs kcwws I,-, V,,, Word/Byte Write or Block Erase Suspend Current 1 10 200 llA VCCW=VCcwHll2 Rev. 1.76 SHARI= LHF32JO2 D`C Charact istics (Continued) eri V,,=2.7V-3.6V Notes c Min. Max. 6 -0.5 0.4 6 Vcc T T Unit V Test Conditions Sym. V, VII-I vo, Parameter Input Low Voltage Input High Voltage Output Low Voltage +0.5 0.4 56 6 46 2.7 7 7 Vcc=Vcc Min. ycc=Vcc Min. I nr =2.omA I I OH=lOOpA `OH Output High Voltage V,, Lockout during Normal Operations Vccw during Block Erase,Full'Chip Erase.Word/Byte Write or Lock-Bit Configurationbperations V,,, during Block Erase,Full Chip Erase,Word/Byte Write or Lock-Bit ConfigurationOperations V,, Lockout Voltage I `CCWLK 1.0 3.6 V V `CCWHl `CCWHZ 11.7 12.3 V VLKO I 2.0 V [OTES: All currentsarein RMS unless otherwisenoted.Typical valuesat nominalVcc voltame T,=+25"C. and I,-,, andI,,,, are specifiedwith the device de-selected. reador word/byte writtt& while in erasesuspend If mode,the device's current draw is the sumof ICC,, or I,,, and ICCR I,,, or respectively. IncludesRYlBY#. Block erases, chip erase. full word/byte writes and lock-bit configurationsare inhibited when VccwSVcc~K. andnot guaranteed the rangebetweenVCCwLK(max.)and VCCWH,(min.),betweenVCCwH,(max.) and Vccwt&min.) and in above VccwB.,jmax.). The Automatic Power Savings(APS) feature is placed automaticallypower savemodethat addresses switching more not than 300nswhile readmode. Sampled,not 100%tested. Applying 12V&.3V to Vccw during erase/writecan only be donefor a maximumof 1000cycles on eachblock. Vccw may be connected 12Vti.3V for a total of 80 hoursmaximum. to 1 Rev. 1.25 SHARP LHF32JO2 6.2.4 AC CHARACTERISTICS Svm. fA.lA,l tAtrOV tELOV -33 - READ-ONLY V ,,=2.7V-3.6V. Parameter OPERATIONS(*) T,=O"C to +7O"C 1 Notes 1 Min. 90 1 Max. 90 90 600 40 0 40 0 15 0 90 25 5 1 Unit I ns ns ns ns ns ns ns ns ns ns ns ns ns I I taun.7 tGLOV tcr nv tEHOZ tGLOX kHOZ tOH tFvov tr;r A? tcr lx, Time Address to Output Delay CE# to Output Delay RP# High to Outuut Delav 1OE# to Output Delay 1CE# to Outnut in Low Z CE# High to Output in High Z OE# to Output in Low Z OE# High to Output in High Z . ' Output Hold from Address, CE# or OE# Change. Whichever Occurs Fist ) BYTE# to Output Delay I BYTE# Low to Outnut in High Z I CE# to BYTE# Hiah or Low I Read Cvcle I 2 [ 2 3 3 3 3 3 I I I I I 3 3 3.4 I I I I 1. 2. 3. 4. See AC Input/Output Reference Waveform for maximum allowable input slew rate. OE# may be delayed up to tELQV-bLQV after the falling edge of CE# without impact on tELQv. Sampled, not 100% tested. If BYTE# transfer during reading cycle, exist the regulations separately. Rev. 1.25 SHARP LHF32JO2 34 -- Standby iDDRESSES Device Address Selection Address Stable Data Valid ___________ ___________ wE#fW) :,I---VOH kLQV kLQV ' l DATNDIQ) :DQvDQd VOL HIGH Z ___________ tAVQV IPHQV Figure 16. AC Waveform for Read Operations Rev. 1.25 SHARI= LHF32JO2 35 II Standby hH ADDRESSES(A) VIL Device Address Selection Data Valid VIH CE#03 VU VIH OEWG) VU hH BYTE#Fl VU VOH DATA(D/Q) (DQo-DQ7) VOL kl.QZ VOH DATAIDIQ) HIGH VOL Z HIGH Z l (DQs-DQIs) Figure 17. BYTE# timing Waveform Rev. 1.25 LHF32JO2 6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS(I) \IoTEs: 1. Read timing characteristics during block erase, full chip erase. word/byte write and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 1. Sampled, not 100% tested. 5. Refer to Table 4 for valid A,, and D,, for block erase. full chip erase. word/byte write or lock-bit configuration. 1. Vccw should be held at VCCWHI,Z until determination of block erase. full chip erase, word/byte write or lock-bit configuration success (SR. l/3/4/5=0). 5. If BYTE# switch during reading cycle, exist the regulations separately. Rev. 1.25 SHARP LHF32JO2 37 -- rVIII ADDRESSES(A) VU VIH CE#(E) VU VIH 1 e----w 2 3 I 5 6 OE#(G) VU WE#(W) DATACDIQ) BYTE#O n-Es: VCC power-up and standby. Write each setup command. Write each confirm command or valid address and data Automated eraSe or program delay. Read statlls register data. Write Read Array command. Figure 18. AC Waveform for WE#-Controlled Write Operations Rev. 1.25 SHARP LHF32JO2 38 -- 6.2.6 ALTERNATIVE CEKCONTROLLED WRITES(*) VOTES: 1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. 5. Refer to Table 4 for valid A,, and D,, for block erase, full chip erase, word/byte write or lock-bit configuration. t. V,,, should be held at VCCWH1,2 until determination of block erase. full chip erase, word/byte write or lock-bit configuration success (SR. l/3/4/5=0). j. If BYTE# switch during reading cycle, exist the regulations separately. Rev. 1.26 SHARP LHF32JO2 39 -- I -e-v-ADDRESSES(A) 2 3 4 5 6 DATACDIQ) NOTES: 1. Vcc power-up and standby. 2. Write each setup command. 3. Write each confirm command or valid address and data. 4. Automated emse or program delay. 5. Read status register data. 6. Write Read Array command. Figure 19. AC Waveform for CE#-Controlled Write Operations Rev. 1.25 SHARP LHF32JO2 6.2.7 RESET OPERATIONS Hieh Z RYiBY#(R)(`b GR.7) VOL ("0") VIH RwP) VIL (A)ResetDuringRead RY/BY#(R) (SR.7) Hieh Z (`?", VOL ("0") VIH =wP) VIL Amy Mode (B)Reset During 2.7V vcc VIL VIH ~+w) VIL Block Erase, Full Chip Erase, Word/Byte L I tZVPH I I Write or Lock-Bit Configuration (C)RP# rising Timing Figure 20. AC Waveform for Reset Operation Reset AC Specifications Sym. tPLPH tPLRZ Parameter RP# Pulse Low Time RP# Low to Resetduring Block Erase,Full Chip Erase, Word/Byte Write or Lock-Bit Configumtion V,, 2.7V to RP# High Notes 2 I,2 Min. 100 M&X. 30 Unit ns PS 100 ns 233 t2VPH NOTES: 1. If RP# is asserted while a block erase,full chip erase,word/byte write or lock-bit configuration operationis not executing, the resetwill completewithin 1OOns. 2. A resettime, tpH v, is requiredfrom the later of RY/BY#(SR.7) going High Z("1") or RP# going high until outputsare valid. Refer to A8 Characteristics Read-Only Operationsfor tpHQv. 3. When the device power-up,holding RP#low minimum 1OOns requiredafter V,, hasbeenin predefinedrangeand also is hasbeenin stablethere. I Rev. 1.25 -- LHF32J02 41 6.2.8 BLOCK ERASE, CONFIGURATION FULL CHIP ERASE, PERFORMANCEt3) WORD/BYTE WRITE AND LOCK-BIT V,,=2.7V-3.6V. Sym. ~WHQV~ Parameter Word Write Time Byte Write Time 1Block Write Time (In word mode) Block Write Time (In byte mode) 32K word Block 4K word Block 64K byte Block I8K byte Block ( 32K wordBlock I I4K word Block 64K byteBlock SK byte Block 32K word Bloc.I:K I_ 64K byte Block 4K word Block 8K bvte Block T ,=O"C to +7O"C V ,,=2.7V-3.6V Notes Typ."' Max. 2 2 2 2 2 2 2 2 2 2 33 36 31 32 1.1 0.15 -a* L.L 0.3 1.2 0.6 1 84 56 I 6 16 1 I 1 200 200 200 200 4 0.5 `) I 1 6 5 420 200 5 15 30 1 Vccw=l 1.7V-12.3V Typ.' " Max. 20 27 19 26 0.66 0.12 1* 1.4 0.25 0.9 0.5 6-t 42 0.69 6 16 1.5 30 1 Unit W US US tEHQVl ) 1 ( 1 1 I 1 1 1 I1 1 I ! I 1 1 I 1 1 I 1 I us S I S S S 1 I I tWHQV?_ `EHQV2 Block Erase Time 1 I 1 IsI S I t 1Full Chin Erase Time 1 2 2 2 4 4 I s US S !Js P I tWHQL'3 Set Lock-Bit Time tEHOV3 WHQVJ Clear Block Lock-Bits Time 1 tEHOV-! b-RZ tEHRZl Word/Byte Write Suspend Latency Time to Read Block Erase Suspend Latency Time to Read twnnz2 tEHRZ2 VOTES: 1. Typical values measured at T,=+25"C and V,,=3.OV, V,,,- -3 OV or 12.OV. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. Sampled but not 100% tested. 4. A latency time is required from issuing suspend command(WE# or CE# going high) until RY/BY# going High Z or SR.7 going "1". Rev. 1.25 SHARF' 7 Package and packing specification 1. Package Outline Specification Refer to drawing No.AA 2. Markings 2 - 1. Marking contents (1) Product name : ( 2 > Company name : (3) Date code (Example) _ LHF32J02 -- 1142 LH28F320BJE-PTTL90 SHARP - Denotes the product ion ref .code (1-S) Denotes the product ion week. (Lower two digit of the year.) w Denotes the product ion ref .code (No marking , A , B , C ) (4) "JAPAN" is marked on the package when both wafer and assembly processes are done in Japan , indicating the country of origin. 2-2. Marking layout Refer drawing No.AAl 14 2 (This layout does not define the dimensions of marking character and marking position.) 3. Packing Specification (Dry packing for surface mount packages) Dry packing is used for the purpose of maintaining IC quality after mounting packages on the PCB (Printed Circuit Board). When the epoxy resin which is used for plastic packages is stored at high humidity, it may absorb 0.15% or more of its weight in moisture. If the surface mount type package for a relatively large chip absorbs a large amount of moisture between the epoxy resin and insert material (e.g. chip, lead frame) this moisture may suddenly vaporize into steam when the entire package is heated during the soldering process (e.g. VPS). This causes expansion and results in separation between the resin and insert material, and sometimes cracking of the package. This dry packing is designed to prevent the above problem from occurring in surface mount packages. 3 - 1. Packing Materials Material Specificaiton Purpose Mater ial Name Conductive plastic (50devices/tray) Fixing of device Tray -_--____________________________________-~--------------------------------------------------------------.-------------------------------------------------------Upper cover tray Conductive plast ic (ltray/case) Fixing of device. ________________________________________~~--------------------------------------------------------------.-------------------------------------------------------~ Laminated aluminum bag Aluminum polyethylene (lbag/case) Drying of device -_______________________________________-~----------------------------------------------------------------------------------------------------------------------. Desiccant Silica gel. Drying ________________________________________-.--.-----------------------------------------------------------.of device ____________________----------------------------------~ P P band Polypropylene (3pcs/case) Fixing of tray -----_--________________________________-.--------------------------------------------.---------------.____________________-----------------------------------. Inner case Card board (500device/case) Packaging of device ----------______________________________---------------------------------------------------------------. --------------------------------------------------.-----. Label Paper Indicates part number,quantity and date of manufacture -----------___________________________________________________________________________________________________________ --______--. Outer case Card board Cuter packing of tray (Devices shall be placed into a tray in the same direction.) SHARP 3-2. Outline dimension Refer to attached of tray drawing LHF32J02 43 4. 4-l. Storage and Opening of Dry Packing Store under conditions shown below before opening the dry packing ( 1) Temperature range : 5%40C : 80% RH or less (2) Humidity Notes on opening the dry packing (1) Before opening the dry packing, prepare a working table grounded against ESD and use a grounding strap. (2) The tray has been treated to be conductive or anti-static. device is transferred to another tray, use a equivalent 4-2. which is If the tray. 4 - 3. Storage after opening the dry packing Perform the following to prevent absorption of moisture after opening. (1) After opening the dry packing, store the ICs in an environment with temperature of 5~25C and a relative humidity of 60% or less and mount ICs within 72 hours after opening dry packing. Baking (drying) before mounting ( 1) Baking is necessary (A) If the humidity indicator in the desiccant becomes pink (B) If the procedure in section 4-3 could not be performed ( 2) Recommended baking conditions If the above conditions (A) and (B) are applicable, bake it before . mounting. The recommended conditions are 16-24 hours at 120C. Heat resistance tray is used for shipping tray. 5. Surface Mount Conditions Please perform the following quality. a conditions when mounting ICs not to deteriorate IC 5-l.Soldering conditions(The following conditions are valid only for one time soldering.) Measurement Point Mounting Method Temperature and Duration IC package Reflow soldering Peak temperature of 230C or less, surface duration of less than 15 seconds. (air) 200C or over,duration of less than 40 seconds. Temperature increase rate of l--4Vsecond ------"--`-------"--------------~-------~-----------------------------------------------------------------------------.----------------------------------. IC outer lead Manual soldering 260C or less, duration of less surface than 10 sec.onds. (soldering iron) 5 - 2. Conditions for removal of residual (1) Ultrasonic washing power (2) Washing time (3) Solvent temperature flux : 25 Watts/liter or less : Total 1 minute maximum : 15-40C SHARP LHF32J02 LH28F320BJE-PTTL90 ! 25 f /SEE DETAIL A DETAIL A PKG.BASE PLANE &zg : UJAPAN.lJ 4ZZSb5%&~7---3R% NOTES Marking specification when "JAPAN"is marked. : 5% j !J- F&-k ! TIN-LEAD (!$@$ -1 jXf7 9W-`i#fj$klt,DJ ~$Wyltf'~ o AME/ TSOP48-P-1220 LEADFINISH i PLATING NOTE Plastic body dimensions do not include burr of resin. 4-G ; DRAWING NO. 1 AA1142 UNIT ; mm SHARP LHF32J02 LH28F320BJE-PTTL90 ZYYWW xxx PKG.E?ASE PLANE jgz $.??%Wti~~~Q0~---3ttt~ OTES: Marking specificat ion when "JAPAN" is not marked. !l - ~tkk i TIN-LEAI: W$ `15ZSr3~Wi?#;tlt;ti, r?J t%dtbC$Who &;i ME! TSOP48-P-1220 LEADFINISH ! PLATING NOTE Plastic body dimensions do not include burr SE i of resin. RAWING NO. j AA1142 UNIT j mm : UJAPANfl J SHARP LHF32J02 q .MEjTSOP48-1220TCM-RH 1RAWINCNO. i CV756 SfC UNIT ; i mm twit NOTE SHARP Gupplementary data) LHF32J02 LHF32.JOZ Recommended mounting Product name(Package) ._ Packing specification Mounting method Reflow soldering conditions conditions for two time reflow soldering . LH28F320BJE-PTTL90(TSOP48-P-1220) Tray (Dry packing) Reflow soldering (Air) Peak temperature of 230C or less. 200C or over, duration of less than 40 seconds. Preheat temperature of 125%150"Cduration of less than 180 seconds. Temperature increase rate of l--4Wsecond. IC package surface After opening the dry packing, store the ICs in an environment with a temperature of 5-25C and a relative humidity of 60% or less. If doing reflow soldering twice,do the first reflow soldering within 72 hours after opening dry packing and do the second reflow soldering within 72 hours after the first reflow soldering. If the above storage conditions are not applicable, bake it before reflow soldering. The recommended conditions are 16-24 hours at 120C. (Heat resistance tray is used for shipping tray.) Measurement point Storage conditions llote Recommended Reflow Soldering(Air) Temperature Profile Peak temperature lime (NO. 000323-X21) SliARP ADDITIONAL INFOFtMATION 1 Block Erase Suspend and Resume command If the time between writing the Block Erase Resume command and writing the Block Erase Suspend command is shorter than 15ms and both commands are written repeatedly, a longer time is required than standard block erase until the completion of the operation. Rev. 0.11 SHARP `I RELATED DOCUMENT lNFOFWlATION(`) Document Name 1 Flash Memory Family Sofhvare Drivers 1 Data Protection Method of SHARP Flash Memory RP#, Vpp Electric Potential Switching Circuit I I Document No. I AP-00 l-SD-E ~ 1 AP-006-R-E AP-007~SW-E NOTE : 1. international customers should contact their local SHARP or distribution sales office. |
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